March 29, 2021
A technology can become well-known from a relatively narrow professional field. There are historical reasons and it is also inseparable from the promotion of famous companies. It is Apple that brings SiP to the public, and advanced packaging can attract widespread public attention. Because TSMC (TSMC).
Apple said that my i Watch uses SiP technology, and SiP has been widely known since then; TSMC said that in addition to advanced technology, I also want to engage in advanced packaging, and advanced packaging has been mentioned by the industry as having the same important status as advanced technology.
In recent years, advanced packaging technologies have continued to emerge, and new terms have also emerged one after another, making people a little dazzling. At present, there are at least dozens of advanced packaging-related names that can be listed.
For example: WLP(Wafer Level Package), FIWLP(Fan-in Wafer Level Package), FOWLP(Fan-Out Wafer Level Package), eWLB(embedded Wafer Level BallGrid Array), CSP(Chip Scale Package), WLCSP(Wafer Level Chip) Scale Package), CoW(Chip on Wafer), WoW(Wafer on Wafer), FOPLP(Fan-Out Panel Level Package), InFO(Integrated Fan-Out), CoWoS(Chip-on-Wafer-on-Substrate), HBM (High-Bandwidth Memory), HMC(Hybrid MemoryCube), Wide-IO(Wide Input Output), EMIB(Embedded Multi-Die Interconect Bridge), Foveros, Co-EMIB, ODI(Omni-Directional Interconnect), 3D IC, SoIC , X-Cube...etc...These are all advanced packaging technologies.
How to distinguish and understand these dazzling advanced packaging technologies? This is what this article will tell the reader.
First of all, in order to facilitate the distinction, we divide advanced packaging into two categories: ① Advanced packaging technology based on XY plane extension, mainly through RDL for signal extension and interconnection; ② Advanced packaging technology based on Z-axis extension, mainly through TSV performs signal extension and interconnection.
Advanced packaging technology based on XY plane extension
The XY plane here refers to the XY plane of the wafer or chip. The distinctive feature of this type of package is that there is no TSV through silicon via. The signal extension method or technology is mainly realized by the RDL layer. Usually there is no substrate, and the RDL wiring is Attached to the silicon body of the chip, or attached to Molding. Because the final package product does not have a substrate, this type of package is relatively thin and is currently widely used in smart phones.
FOWLP (Fan-out Wafer Level Package) is a kind of WLP (Wafer Level Package), so we need to understand WLP wafer level package first.
Before the advent of WLP technology, the traditional packaging process steps were mainly carried out after dicing and slicing the die. The wafer was firstly diced and then packaged into various forms.
WLP came out around 2000. There are two types: Fan-in (fan-in) and Fan-Out (fan-out). WLP wafer level packaging is different from traditional packaging. In the packaging process, most of the processes are correct. The wafer is operated, that is, the overall packaging (Packaging) is performed on the wafer, and the dicing is performed after the packaging is completed.
Since the dicing is performed after the packaging is completed, the packaged chip size is almost the same as that of the bare chip, so it is also called CSP (Chip Scale Package) or WLCSP (Wafer Level Chip Scale Packaging). This type of package conforms to consumer products. The market trend of electronic products being light, small, short and thin, parasitic capacitance and inductance are relatively small, and they have the advantages of low cost and good heat dissipation.
At the beginning, WLP mostly adopts the Fan-in type, which can be called Fan-in WLP or FIWLP, which is mainly used in chips with a small area and a small number of pins.
With the improvement of IC technology, the chip area shrinks, and the chip area cannot accommodate enough pins. Therefore, the Fan-Out WLP package form, also known as FOWLP, is derived, which realizes the full use of RDL outside the chip area to make connections. Get more pins.
FOWLP, because RDL and Bump are to be led out to the periphery of the bare chip, it is necessary to dicing the bare chip wafer first, and then reconfigure the independent bare chip into the wafer process, and on this basis, through batch Process and metalize the wiring interconnections to form the final package. The FOWLP packaging process is shown in the figure below.
FOWLP is supported by many companies, and different companies have different naming methods. The following figure shows the FOWLP provided by major companies.
Whether it is Fan-in or Fan-out, the connection between WLP wafer-level packaging and PCB is in the form of flip-chip, and the active side of the chip faces the printed circuit board, which can achieve the shortest electrical path, which also guarantees A higher speed and less parasitic effects. On the other hand, due to the use of batch packaging, the entire wafer can be packaged all at once, and cost reduction is another driving force for wafer-level packaging.
InFO (Integrated Fan-out) is an advanced FOWLP packaging technology developed by TSMC in 2017. It is an integration on the FOWLP process, which can be understood as the integration of multiple chip Fan-Out processes, while FOWLP focuses on Fan -Out packaging process itself.
InFO has given space for the integration of multiple chips, which can be applied to the packaging of radio frequency and wireless chips, the packaging of processors and baseband chips, and the packaging of graphics processors and network chips. The figure below is a comparison diagram of FIWLP, FOWLP and InFO.
Apple’s iPhone processor was always produced by Samsung in the early years, but TSMC started from Apple’s A11 and took orders for two generations of iPhone processors one after another. Connect, reduce the thickness, free up valuable space for batteries or other parts.
Apple has started InFO packaging from iPhone 7, and will continue to use it in the future. iPhone 8, iPhone X, including other brands of mobile phones in the future will also begin to use this technology. The addition of Apple and TSMC has changed the application status of FOWLP technology, which will enable the market to gradually accept and generally apply FOWLP (InFO) packaging technology.
The FOPLP (Fan-out Panel Level Package) panel level package draws on the ideas and technology of FOWLP, but uses a larger panel, so it can produce packaged products that are several times the size of 300 mm silicon wafer chips.
FOPLP technology is an extension of FOWLP technology. The Fan-Out process is performed on a larger square carrier board, so it is called FOPLP packaging technology. Its Panel carrier board can be a PCB carrier board or a glass carrier board for liquid crystal panels.
At present, FOPLP uses a PCB carrier such as 24×18 inches (610×457mm), and its area is about 4 times that of a 300 mm silicon wafer. Therefore, it can be simply regarded as a single process, which can be measured. Produce advanced packaging products that are 4 times the size of 300 mm silicon wafers.
Like the FOWLP process, the FOPLP technology can integrate the pre- and post-encapsulation process, which can be regarded as a one-time packaging process, so it can greatly reduce the costs of production and materials. The figure below shows the comparison between FOWLP and FOPLP.
FOPLP uses PCB production technology for RDL production. Its line width and line spacing are currently greater than 10um. SMT equipment is used to mount chips and passive components. Since its panel area is much larger than the wafer area, it can be used once Package more products. Compared with FOWLP, FOPLP has a greater cost advantage. At present, major global packaging companies including Samsung Electronics and ASE are actively investing in FOPLP process technology.
EMIB (Embedded Multi-Die Interconnect Bridge) advanced packaging technology of embedded multi-die interconnect bridge is proposed and actively applied by Intel. Unlike the three advanced packages described above, EMIB is a substrate type package, because EMIB does not TSV is therefore also divided into advanced packaging technology based on XY plane extension.
The EMIB concept is similar to the 2.5D package based on a silicon interposer, which is a local high-density interconnection through silicon. Compared with the traditional 2.5 package, because there is no TSV, EMIB technology has the advantages of normal package yield, no additional process and simple design.
Traditional SoC chips, CPU, GPU, memory controller and IO controller can only be manufactured using one process. Using EMIB technology, CPU and GPU have high process requirements, and can use 10nm process, IO unit, communication unit can use 14nm process, memory part can use 22nm process, and EMIB advanced packaging technology can integrate three different processes into one A processor. The figure below is a schematic diagram of EMIB.
Compared with silicon interposer (interposer), EMIB silicon chip area is smaller, more flexible and more economical. EMIB packaging technology can package CPU, IO, GPU and even FPGA, AI and other chips together according to needs, and can package chips of different processes such as 10nm, 14nm, 22nm, etc. together into a single chip, adapting to the needs of flexible business .
Through the EMIB method, the KBL-G platform integrates Intel Core processors and AMD Radeon RX Vega M GPUs, and at the same time has the powerful computing power of Intel processors and the excellent graphics capabilities of AMD GPUs, as well as an excellent heat dissipation experience. . This chip has created history and brought the product experience to a new level.
Advanced packaging technology based on Z-axis extension
The advanced packaging technology based on Z-axis extension is mainly for signal extension and interconnection through TSV. TSV can be divided into 2.5D TSV and 3D TSV. Through TSV technology, multiple chips can be vertically stacked and interconnected.
In 3D TSV technology, the chips are very close to each other, so the delay will be less. In addition, the shortening of interconnection length can reduce related parasitic effects and make the device run at a higher frequency, which translates into performance improvement and greater The degree of cost reduction.
TSV technology is the key technology of three-dimensional packaging, including semiconductor integrated manufacturers, integrated circuit manufacturing foundries, packaging foundries, emerging technology developers, universities and research institutes, and technology alliances and other research institutions have carried out many aspects of the TSV process. Research and development.
In addition, readers need to note that although advanced packaging technology based on Z-axis extension mainly uses TSV for signal extension and interconnection, RDL is also indispensable. For example, if the TSVs of the upper and lower chips cannot be aligned, they need to pass RDL performs local interconnection.
CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D packaging technology launched by TSMC. CoWoS is to package the chip on a silicon interposer (interposer), and use high-density wiring on the silicon interposer for interconnection. Connect, and then install it on the package substrate, as shown in the figure below.
Both CoWoS and the aforementioned InFO come from TSMC. CoWoS has a Silicon Interposer, but InFO does not. CoWoS is aimed at the high-end market, and the number of connections and package size are relatively large. InFO targets the cost-effective market, with smaller package sizes and fewer connections.
TSMC began mass production of CoWoS in 2012. Through this technology, multiple chips are packaged together, and through Silicon Interposer high-density interconnection, it has achieved the effect of small package size, high performance, low power consumption, and fewer pins.
CoWoS technology is widely used. Nvidia's GP100 and the Google chip TPU2.0 behind AlphaGo that defeated Ke Jie all use CoWoS technology. The artificial intelligence AI is also behind the contribution of CoWoS. At present, CoWoS has been supported by high-end chip manufacturers such as NVIDIA, AMD, Google, XilinX, and Huawei HiSilicon.
HBM (High-Bandwidth Memory) high-bandwidth memory, mainly for the high-end graphics card market. HBM uses 3D TSV and 2.5D TSV technologies to stack multiple memory chips together through 3D TSV, and uses 2.5D TSV technology to interconnect stacked memory chips and GPUs on the carrier board. The figure below shows a schematic diagram of HBM technology.
HBM currently has three versions, namely HBM, HBM2 and HBM2E, with bandwidths of 128 GBps/Stack, 256 GBps/Stack and 307 GBps/Stack respectively. The latest HBM3 is still under development.
AMD, NVIDIA and Hynix’s main HBM standard, AMD first used the HBM standard in its flagship graphics cards, with a video memory bandwidth of up to 512 GBps, and NVIDIA followed closely, using the HBM standard to achieve 1TBps of video memory bandwidth. Compared with DDR5, HBM performance is improved by more than 3 times, but power consumption is reduced by 50%.
HMC (Hybrid Memory Cube) hybrid storage cube, its standard is mainly promoted by Micron, the target market is the high-end server market, especially for the multi-processor architecture. HMC uses stacked DRAM chips to achieve greater memory bandwidth. In addition, HMC integrates the memory controller (Memory Controller) into the DRAM stack package through 3D TSV integration technology. The following figure shows the schematic diagram of HMC technology.
Comparing HBM and HMC, it can be seen that the two are very similar. Both stack DRAM chips and interconnect them through 3D TSV, and there are logic control chips under them. The difference between the two is that HBM is interconnected through Interposer and GPU, while HMC is installed directly on Substrate, lacking Interposer and 2.5D TSV in the middle.
In the HMC stack, the diameter of the 3D TSV is about 5-6um, and the number exceeds 2000+. The DRAM chips are usually thinned to 50um, and the chips are connected by a 20um MicroBump.
In the past, memory controllers were built in processors, so in high-end servers, when a large number of memory modules need to be used, the design of the memory controller is very complicated. Now that the memory controller is integrated into the memory module, the design of the memory controller is greatly simplified. In addition, HMC uses a high-speed serial interface (SerDes) to implement a high-speed interface, which is suitable for situations where the processor and memory are far away.
Wide-IO (Wide Input Output) broadband input and output technology is mainly promoted by Samsung. It has reached the second generation. It can achieve a memory interface width of up to 512bit. The operating frequency of the memory interface can reach up to 1GHz, and the total memory bandwidth can reach 68GBps. It is twice the bandwidth of the DDR4 interface (34GBps).
Wide-IO is realized by stacking the Memory chip on the Logic chip, and the Memory chip is connected to the Logic chip and substrate through 3D TSV, as shown in the figure below.
Wide-IO has the advantages of the vertical stacking package of the TSV architecture, which can help create mobile storage with both speed, capacity and power characteristics to meet the needs of mobile devices such as smartphones, tablets, and handheld game consoles. Its main target market is Mobile devices that require low power consumption.
In addition to the EMIB advanced packaging described earlier, Intel also introduced Foveros active onboard technology. In Intel's technical introduction, Foveros is called 3D Face to Face Chip Stack for heterogeneous integration, a three-dimensional face-to-face heterogeneous integration chip stack.
The difference between EMIB and Foveros is that the former is a 2D packaging technology, while the latter is a 3D stacked packaging technology. Compared with 2D EMIB packaging, Foveros is more suitable for small-size products or products with higher memory bandwidth requirements. In fact, EMIB and Foveros have little difference in chip performance and functions. Both chips of different specifications and functions are integrated to play different roles. However, in terms of volume and power consumption, the advantages of Foveros 3D stacking have emerged. The power of the data transmitted by Foveros per bit is very low. The Foveros technology has to deal with the reduction of the Bump pitch, the increase of the density and the chip stacking technology.
The following figure shows the schematic diagram of Foveros 3D packaging technology.
The first Foveros 3D stacked design motherboard chip LakeField, it integrates a 10nm Ice Lake processor and a 22nm core, with complete PC functions, but the size is only a few cents.
Although Foveros is a more advanced 3D packaging technology, it is not a substitute for EMIB. Intel will combine the two in subsequent manufacturing.
10. Co-EMIB (Foveros + EMIB)
Co-EMIB is a complex of EMIB and Foveros. EMIB is mainly responsible for the horizontal connection, so that the chips of different cores are spliced together like a puzzle, while Foveros is a vertical stack, just like a tall building. Each floor can have complete Different designs, such as a gym on the first floor, an office building on the second floor, and an apartment on the third floor.
The packaging technology that combines EMIB and Foveros is called Co-EMIB, which is a more flexible chip manufacturing method that allows chips to continue to be spliced horizontally while being stacked. Therefore, this technology can splice multiple 3D Foveros chips together through EMIB to create a larger chip system. The figure below is a schematic diagram of Co-EMIB technology.
Co-EMIB packaging technology can provide performance comparable to that of a single chip. The key to achieving this technology is ODI (Omni-Directional Interconnect) omni-directional interconnection technology. ODI has two different types. In addition to connecting elevator types on different floors, there are also flyovers connecting different three-dimensional structures, as well as interlayers between floors, so that different chip combinations can have extremely high flexibility. ODI packaging technology allows chips to be interconnected both horizontally and vertically.
Co-EMIB uses a new 3D + 2D packaging method to transform chip design thinking from a flat puzzle in the past to a pile of wood. Therefore, in addition to revolutionary new computing architectures such as quantum computing, CO-EMIB can be said to maintain and continue the best practices of the existing computing architecture and ecology.
SoIC, also known as TSMC-SoIC, is a new technology proposed by TSMC-System-on-Integrated-Chips. It is expected that TSMC’s SoIC technology will be mass-produced in 2021.
What exactly is SoIC? The so-called SoIC is an innovative multi-chip stacking technology that can perform wafer-level integration for processes below 10 nanometers. The most distinctive feature of this technology is the no-bump bonding structure, so it has a higher integration density and better running performance.
SoIC includes two technical forms: CoW (Chip-on-wafer) and WoW (Wafer-on-wafer). From the description of TSMC, SoIC is a direct bond of WoW wafer-to-wafer or CoW chip-to-wafer Bonding technology belongs to Front-End 3D technology (FE 3D), while the aforementioned InFO and CoWoS belong to Back-End 3D technology (BE 3D). TSMC and Siemens EDA (Mentor) collaborated on SoIC technology and launched related design and verification tools.
The figure below is a comparison of 3D IC and SoIC integration.
Specifically, the manufacturing process of SoIC and 3D IC is somewhat similar. The key of SoIC is to realize a junction structure without bumps, and the density of its TSV is higher than that of traditional 3D IC, which can be realized directly by extremely small TSV. The interconnection between layers of chips. The figure above shows the comparison of TSV density and bump size between 3D IC and SoIC. It can be seen that the TSV density of SoIC is much higher than that of 3D IC. At the same time, the interconnection between its chips also adopts no-Bump direct bonding technology. The chip pitch is smaller and the integration density is higher. Therefore, its products are also better than traditional ones. 3D IC has a higher functional density.
X-Cube (eXtended-Cube) is a 3D integrated technology announced by Samsung that can accommodate more memory in a smaller space and shorten the signal distance between units.
X-Cube is used in processes that require high performance and bandwidth, such as 5G, artificial intelligence, wearable or mobile devices, and applications that require high computing power. X-Cube uses TSV technology to stack SRAM on top of the logic unit, which can accommodate more memory in a smaller space.
It can be seen from the X-Cube technology display diagram that, unlike the previous 2D parallel packaging of multiple chips, the X-Cube 3D package allows multiple chips to be stacked and packaged, making the finished chip structure more compact. TSV technology is used to connect the chips, which reduces power consumption while increasing the transmission rate. The technology will be applied to the cutting-edge 5G, AI, AR, HPC, mobile chips, VR and other fields.
X-Cube technology greatly shortens the signal transmission distance between chips, increases data transmission speed, reduces power consumption, and can customize memory bandwidth and density according to customer needs. At present, X-Cube technology can already support 7nm and 5nm processes. Samsung will continue to cooperate with global semiconductor companies to deploy this technology in a new generation of high-performance chips.
Conclusion Advanced packaging technology
In this article, we describe the 12 most mainstream advanced packaging technologies today. The following table is a horizontal comparison of these mainstream advanced packaging technologies.
From the comparison, we can see that the emergence and rapid development of advanced packaging is mainly in the past 10 years. Its integration technology mainly includes 2D, 2.5D, 3D, 3D+2D, 3D+2.5D, and its function density is also low. , Medium, high, and extremely high. Application areas include 5G, AI, wearable devices, mobile devices, high-performance servers, high-performance computing, high-performance graphics and other fields. The main application vendors include TSMC, Intel, SAMSUNG and other famous Chip manufacturers, this also reflects the trend of integration of advanced packaging and chip manufacturing.
Finally, let's summarize: the purpose of advanced packaging is to:
Improve function density, shorten interconnection length, improve system performance, and reduce overall power consumption.
Advanced packaging also puts forward new requirements for EDA tools. EDA tools need to be able to support FIWLP, FOWLP, 2.5D TSV and 3D TSV design, and also need to support multi-substrate design, because a product has a silicon interposer (inteposer) and Packaging substrates (Substrate) are often integrated together, and major EDA companies have launched new tools to support the design and verification of advanced packaging, including Synopsys, Cadence, Siemens EDA (Mentor) are actively participating.
The following figure shows a screenshot of the advanced package design of Siemens EDA XPD tool. The design includes 3D TSV and 2.5D TSV design, Interposer, Substrate, FlipChip, Microbump, BGA and other elements, which are detailed and accurate in the EDA tool.