March 11, 2021
Advanced packaging is playing a bigger role and becoming a more viable option to develop new system-level chip designs, but it also presents chipmakers with a confusing array of options and sometimes a hefty price tag.
Automotive, servers, smartphones and other systems have embraced advanced packaging in one form or another. For other applications, it’s overkill, and a simpler commodity package will suffice. Still, advanced packaging is fast becoming an attractive option for many. The industry is developing new forms of advanced packaging or upgrading the existing technologies for a range of applications, such as 5G and AI.
It has taken the industry years to get to this point. Assembling dies in a rudimentary package has been possible for decades. But as scaling runs out of steam, packaging opens up a whole new set of architectural options that can improve performance, reduce power, and add flexibility into designs to both customize them for specific markets and reduce time to market.
No one package type can meet all needs, however. Each application is different, and each has its own unique requirements. In some cases, advanced packaging may not even be the right solution.
Semiconductor Engineering examined the benefits and challenges of advanced packaging in four markets — servers, networking equipment, smart glasses and military/aerospace. While this is just a sample of the possible applications, it highlights some of the main issues and challenges in packaging that chipmakers will face in the future.
The total IC packaging market was worth $68 billion in 2019, according to Yole Développement. Of that, the advanced packaging industry was $29 billion in 2019 and is expected to grow by 6.6% to reach $42 billion in 2025, according to Yole.
Typically, to advance a leading-edge design, device makers rely on chip scaling. The goal is to pack more functions on a monolithic die at each new process node, with a new node rolling out roughly every 18 to 24 months. But scaling is becoming more difficult and expensive at each node, and the price/performance benefits are diminishing. So while scaling will continue, not all components in a system will scale equally.
“It is really about die economics,” said Walter Ng, vice president of business development at UMC. “At bleeding-edge nodes, wafer costs are astronomical, so few customers and few applications can afford to take advantage of expensive process technology. Even for customers that can afford the cost, some of their die sizes are running up against the maximum reticle size. That, of course, results in yield challenges, which then further exacerbates the cost problem. Customers want a more optimized technical solution, which will deliver a more cost-effective business solution. The amount of time it takes to design and verify a large system-on-a-chip (SoC) at the bleeding edge is also a concern for many from a time-to-market perspective.”
In the server world, this points to both disaggregation — offloading functions that do not require or benefit from the most advanced digital logic — as well as heterogeneous integration using a high-speed die-to-die interconnect. There are a number of options available, but the current buzz is around chiplets.
In chiplets, a chipmaker may have a menu of modular dies, or chiplets, in a library, not all of which have to be developed at the same process node. Generally, a design that includes chiplets resembles a monolithic SoC, but it costs less to develop.
This all sounds good on paper, but there are some challenges. “This is an emerging environment. It’s a new model. There are not a lot of standards when it comes to interfaces. The early adopters of chiplet integration tend to be vertically integrated companies that can control all of the design elements, and specifically the interfaces,” said Eelco Bergman, senior director of business development at ASE, in a presentation at the recent IMAPS2020 conference. “Today, the chiplet designs will be largely driven by a chip developer, whether that’s an IDM or a fabless supplier. As the industry evolves and the ecosystems open up, you’ll see this change.”
Others agreed. “Understanding the bus design and interface specs are really critical. If it’s a proprietary situation, then clearly the customer is going to end up taking a lead role there. That will be true for some time,” said Mike Kelly, vice president of advanced package and technology integration at Amkor, in a presentation. “Once we establish a place where we have common bus architectures that everyone understands and are well specified, then design can be very flexible, whether it’s a vertically integrated company, IDM or an OSAT for that matter.”
AMD, Intel, and a few others have introduced chiplet-like architectures. For example, instead of a large monolithic die, AMD’s latest server processor line integrates smaller dies in a module, sometimes called a multi-chip module (MCM). The chips are connected using a die-to-die interconnect.
Referred to as a 2D chiplet design, AMD’s MCM incorporates an integrated I/O and memory controller die based on a 14nm process. That die is situated in the middle. Eight 7nm processor dies also are incorporated in the MCM. Four processor dies are situated on each side of the I/O die.
Fig. 1: AMD’s EPYC server process with 8 core dies and 1 I/O die Source: AMD
For its server processor lines, AMD moved to a chiplet-like approach for several reasons. “In order to continue the required performance trend of 2X performance every two years, we’re going to need chiplets to not only enable more transistors at better yield, but to reduce the total amount of advanced-node silicon,” said Bryan Black, a senior fellow at AMD, in a presentation.
Going forward, AMD plans to expand its MCM efforts on the server processor front. It also plans to develop chiplets using 3D stacking techniques. “As we move into 3D stacking, we’re going to exacerbate all of these challenges that we’ve been working on in 2D,” Black said.
Both 2D- and 3D-based chiplet designs have many of the same challenges. “Chiplets aren’t free,” Black said. “They do have a cost associated with them, both in a packaging cost and an increase in die area cost. We can’t take a monolithic component with 2X area and divide it into two smaller die that are just 1X area each. There is an overhead when communicating between the two, as well as additional power logic, additional coherency logic, additional clocking controls, and as well as efficient test controls. We have a ton of extra control logic in addition to the I/O communication overhead that is required to connect these two dies and make them look as similar to being as one die as possible.”
On top of that, a package requires dies with good yields, also called known good die. One bad die in the package can lead to product or system failures. “There is parametric variation in all of the dies. And so we have a fundamental test and characterization problem of multi-die solutions. Some are slow. Some are fast. Some consume more or less power,” Black said.
Heat, power distribution, and reliability are also challenges with chiplet-based designs. And then, if the package fails, the big question is who takes responsibility. Is it the chip vendor, the IP supplier or the packaging house?
For this, the packaging industry can learn from past experiences, particularly in the early stages of 2.5D. With 2.5D, dies are stacked or placed side-by-side on top of an interposer. The interposer, which incorporates through silicon vias (TSVs), acts as the bridge between the chips and a board.
In the early stages of 2.5D, device makers were wrestling with different dies, integration issues and yield challenges. Over time, though, vendors worked through the problems.
“I remember when the 2.5D projects started,” Amkor’s Kelly said. “The number one thing that helped us was getting yields up to a point. Then it wasn’t a huge challenge to sort through the few yield losses that you had.”
If a die didn’t meet spec, vendors would then conduct an extensive root cause analysis of the device. This requires a sound testing strategy.
The same type of recipe could be implemented for heterogenous integration using chiplets. As before, developing dies with good yields is critical. “You are going to take it to another extreme. You will have more dies and more solder joints. But as long as your fundamental assembly process is rock solid, it’s not going to be as painful of a discussion as we found it with 2.5D,” Kelly said.
Indeed, the package must have good yields at acceptable costs. But when a failure occurs, it goes back to the supplier. “At the end of the day, the supplier is the one that’s ultimately responsible for the product. But the supply base that supported that chip supplier is there to help in that failure analysis process. Once that is identified, then the liabilities and responsibilities become much more clear,” ASE’s Bergman said.
The goal is to prevent failures in the first place. That takes a holistic approach starting with the design. “Through the design phase, we will figure out what’s going to work best with the customer,” said Ken Molitor, chief operating officer at Quik-Pak. “We’ll turnkey the entire project, where we design the substrate, have the substrate fabricated, and then come up with a cohesive design. Then, we will have it assembled. There are certain milestones (during the process.) That tends to reduce the risk on his end and in our end.”
Networking equipment vendors face many of the same challenges. The network is a complex system that spans from the home office to the cloud. To address these markets, communication equipment vendors sell different systems for various parts of the network.
For example, in one part of the network, Cisco sells a router for large-scale service providers. A router directs the network using IP data packets. Cisco’s latest router is based on its own, in-house ASIC. Built around a 7nm process, Cisco’s monolithic ASIC enables 12.8 Tbps of bandwidth on the same chip.
Cisco also develops ASICs for its other networking products. Other communication equipment vendors develop ASICs, as well.
Vendors also are exploring or implementing alternative approaches for several reasons. At each node, the ASIC is becoming bigger and more expensive. It also incorporates a SerDes (serializer/deserializer), which provides high-speed chip-to-chip communications.
“Network bandwidth scaling requirements result in an increase in networking ASIC die size with every technology generation,” said Valery Kugel, a senior distinguished engineer at Juniper, in a presentation. “(The) SerDes is occupying a large portion of the ASIC area.”
There are other issues. The ASIC consists of both digital and analog blocks. The digital portion benefits from scaling, enabling more functions with higher bandwidths. But not everything benefits from scaling.
“The SerDes function is not shrinking. That is an analog structure. It doesn’t scale well,” said Nathan Tracy, a technologist and manager of industry standards at TE Connectivity. Tracy is also the president of the Optical Internetworking Forum (OIF), an industry standards group.
There are several solutions here, including chiplets. To connect dies in a package, OIF is developing a die-to-die interface standard called CEI-112G-XSR. XSR connects chiplets and optical engines in MCMs. It enables data rates up to 112Gbps over a short reach link. XSR is still in the draft form.
There are several ways to implement chiplets and XSR in networking equipment. For example, the large ASIC is split into two smaller dies, which are connected using an XSR link.
In another example, the large SerDes block is broken up into four smaller I/O dies. Then, in an MCM, the ASIC sits in the middle, which is surrounded by four smaller I/O chiplets.
Fig. 2: Example of an Ethernet switch SoC requiring die-to-die connectivity. Source: Synopsys
In addition, a device maker could integrate optical engines with a switch chip ASIC in an MCM.
“There’s a lot of industry buzz about co-packaged optics,” Tracy said. “I’m talking about the possibility of moving away from pluggable optical transceivers at the face blade of the switch to having the optical engine mounted directly on the switching silicon. You need a low-power high-speed interconnect. The focus of that discussion is OIF’s XSR development.”
The adoption of chiplets will depend on the application. In some cases, ASICs still make sense. There are several factors here, such as cost and yield. “It’s all about reducing power consumption,” Tracy said.
“Use of chiplets allow decreasing the main die size to fit within the reticle size limits. But most ICs are not reticle limited. So this argument only works for a very small number of ICs. It’s a strong argument that doesn’t apply to most designs,” according to one expert. “If you split the design in two, you get 2X the number of die per wafer. Assuming the defects ‘D’ per wafer are relatively constant, then your yield goes from X-D to 2X-D. Of course, it takes twice as many die per package, so your effective yield is (2X-D)/2 = X-D/2. You have effectively cut the defects in half at the cost of a more complex two die versus one die package. As multi-die packaging technology improves over time, this will be less of an issue.”
These solutions may work for networking gear, but the consumer market has different requirements, especially for new and emerging products.
For example, in R&D, several companies are developing next-generation smart glasses or AR/VR glasses. Virtual reality (VR) enables users to experience 3D virtual environments. Augmented reality (AR) takes computer-generated images and overlays them on the system.
If the technology works, AR/VR glasses could be used for data retrieval, face recognition, games and language translation. They also could project a presentation or a keyboard on a surface.
“[AR/VR] and their variant devices are only at the beginning of their journey to become the next-generation computing platform,” said Chiao Liu, director and research scientist at Facebook Reality Labs, in a paper at last year’s IEDM.
Developing a useful and inexpensive pair of smart glasses isn’t a simple task. These products require new low-power chips, displays and interfaces. In these glasses, the programs are activated using voice, eye gaze, and head/body movements. All of these technologies must be secure.
“We are going to need dramatic improvements across the board,” said Ron Ho, director of silicon engineering at Facebook, in a presentation at IMAPS2020. “I need a lot more performance relative to power than I am able to sustain in systems today. Generally, I need to run things faster with lower latency.”
To enable smart glasses at the right form factor, IC packaging is key. “I have to manage packages that enable things like increased performance and lower latency,” Ho said. “You can’t force chips to go over a multi-inch trace and burn a bunch of power on PCIe. But rather you co-package them and put them next to each other. And through TSVs, they have a much higher bandwidth and higher performance connections.”
At IEDM, Facebook disclosed some clues about its AR/VR glasses, which are in R&D. In a paper, Facebook outlined the development of a computer vision interface technology for AR/VR glasses. The underlying technology is an advanced CMOS image sensor.
CMOS image sensors provide the camera functions in smartphones and other products. But standard image sensors aren’t adequate for AR/VR glasses. What’s required are machine-perception optimized image sensors with advanced packaging. In the paper, Facebook described a three-layer image sensor. The first layer is an image sensor with a processing unit, followed by an aggregation processor, and then a cloud compute platform.
Facebook also mentioned copper hybrid bonding. For this, the dies are stacked and connected using a copper-to-copper diffusion bonding technique. It’s unclear if Facebook will go down this route, but hybrid bonding is a known technology in the image sensor world.
For decades, meanwhile, the U.S. Department of Defense (DoD) has recognized that chip technology is essential for U.S. military superiority. For various systems, the defense community uses chips at both advanced and mature nodes. Packaging is also a critical part of the equation.
Military/aerospace involves a multitude of customers with different requirements, although there are some common themes here. “We service a lot of different sectors,” Quik-Pak’s Molitor said. “We do service the mil/aero industry. The mil/aero programs tend to be long-lived. They are used to dealing with components that have to work for 20 to 30 years.”
Mil/aero customers face other challenges. As with the commercial sector, the cost of developing advanced chips is expensive, but the benefits are shrinking at each node. Plus, the volumes are relatively low for the defense community.
At times, the defense community uses non-U.S. foundries to obtain advanced chips, but it prefers to use onshore vendors for security purposes. Mil/aero customers want a trusted and assured supply chain for both chips and packages.
Nonetheless, the DoD is looking for alternative approaches beyond chip scaling, namely heterogenous integration and chiplets.
For example, Intel was recently awarded a new contract for the DoD’s new chiplet effort, called the State-of-the-Art Heterogeneous Integration Prototype (SHIP) program. Under the plan, Intel has established a new U.S. commercial entity around chiplets. This program gives customers access to Intel’s packaging capabilities, including the DoD and the defense community.
There are various parts to the SHIP program. While Intel won the digital portion of the program, Qorvo was awarded the RF part of the SHIP project. Under that project, Qorvo will set up an RF heterogeneous packaging design, production and prototyping center in Texas. This center will primarily serve the defense community.
Qorvo isn’t new to mil/aero. For years, the supplier of RF devices and other products provides both foundry and packaging services for mil/aero and the commercial sector. The company develops devices based on gallium nitride (GaN), gallium arsenide (GaAs) and other processes.
In mil/aero, the packaging requirements have changed over the years. “When I first started working for Qorvo many years ago, nobody wanted us to send them packaged parts. Mil/aero wanted bare die,” said Dean White, director of defense and aerospace market strategy at Qorvo. “We’ve seen the market change from a military-aerospace type market, which is bare die, to packaging and packaging integration. Packaging is more environmentally robust than it was years ago. We do a lot of packaging for mil/aero in a variety of different packages, depending upon power levels, heat dissipation and robustness for vibration.”
Under the SHIP program, Qorvo will provide heterogenous packaging services using devices based on GaN, GaAs and silicon. The goal is to meet what the DoD calls SWAP-C, an acronym that denotes the size, weight, power and cost requirements for packages in various applications, such as phased-array radar systems, unmanned vehicles, electronic warfare platforms and satellites.
The SHIP program is geared for packaging, although Qorvo will provide a one-stop shop. It will continue to provide foundry and packaging services for mil/aero customers. “We’re modeling it after our foundry model. We’re using the same kind of open access type of model. And this would be a service. You could design in our foundry. And then you could say, ‘Can you take those parts and then put them into a package?’ So this is an addition or expansion of our current capability,” White said.
Meanwhile, mil/aero involves custom work. Each customer may have different packaging requirements with various challenges.
Take RF, for example. “One of the challenges that you have in the RF community is, once you put a device into a package, it changes the RF performance,” White said. “You have to design your chips and your MMICs to fit inside these packages, and to perform as close as you possibly can to their original intended performance.”
With that in mind, developing a chiplets model around RF is easier said than done. “(SHIP) is targeted to use GaN, GaAs and silicon. They will also all be integrated inside of these heterogeneous packages,” White said. “The higher in frequency you go, the more challenging it becomes to do a chiplet-type design. That’s one of the areas that we’re exploring as part of SHIP. This is doing what the government would call a chiplet-type of a design. And that’s not been completely defined yet.”
There are plenty of other markets that are expected to push toward more heterogeneous integration. Apple’s low-end Mac computers are moving to an internally developed M1 processor that integrates CPU cores, graphics, a machine learning engine in a “customized package,” according to the company.
That is just the beginning, too. There are new opportunities for packaging in other markets, such as 5G, AI, mobile, and plenty of challenges to go along with them. But there appears to be no shortage of opportunity to keep the industry busy, amid the new and monumental changes taking place in the market.(From Mark LaPedus)