News

CSP packaging substrate
CSP (Chip Scale Packages)
Chip Scale Packaging (CSP) utilizes fine pattern technology, very small via's, ultra thin copper foil and build up structure for high density designs and flexibility. The CSP substrate provides high reliability in both connection and isolation.
 

Features

Fine patterning technology for high density design
 Build up structure for high design flexibility
High reliability in connection and isolation
Adoption of low CTE material suitable for PoP

Material BT Resin

Layer count 2~6

Line and Space 0.020mm / 0.020mm

Package Size 3x3mm ~ 19x19mm

Board Thickness 0.13mm

FCCSP packaging substrate
FC-CSP (Flip Chip) CSP
Flip Chip CSP (FC CSP) utilizes flip chip bumping technology instead of wire bonding to connect the bump pads on the substrate directly to the bonding pads of the chip. With the high density layout and smaller package size, this technology provides cost reductions.
 

Features

High I/O Count and Short Interconnects.
 High layout density.
Cost reduction due to smaller package size.
Fine pattern & Fine Bump Pitch
Tight solder resist position tolerance
Flip Chip Bumping Technology

Material BT Resin

Layer count 2~6

Line and Space 0.020mm / 0.020mm

Bump Pitch 0.15mm

Micro Via and Land 0.065mm / 0.135mm

PBGA packaging substrate

Plastic Ball Grid Array (PBGA) connects the Chip to the substrate and encapsulates it with a plastic molding compound. The optimized substrate design provides enhanced thermal and electrical performance and dimensional stability to package on package.

Features

Optimization of substrate design considering thermal and electrical performance
Finer ball pitch and thinner package thickness
High electrical performance due to short wire length
 Etch back process
 Available both for Flip-chip & Wire bonding
High density wiring by Semi-additive process
Fine pattern formation to bond on trace technology
Substrate dimension stability to package on package
Leadless plate design for interconnection

Material BT Resin

Layer count 2~6

Line and Space 0.020mm / 0.020mm

Package Size 21x21mm ~ 35x35mm

Board Thickness 0.21mm

BOC packaging substrate
BOC (Board on Chip)
Board On Chip (BOC) designs have the substrate bonded to the circuit side of the die, and wire bonds are connected between the conductors of the substrate and the bond pads on the die.
 

Features

Punched slots for Low cost and High Accuracy position
Low cost routed slots
Fine patterning technology for high density design
Reduce signal noise by using a short electrical path

Material BT Resin

Layer count 2~4

Line and Space 0.030mm / 0.030mm

Slot Size Tolerance +/-0.05mm

Board Thickness 0.13mm

FMC packaging substrate
FMC (Flash Memory Card)
Flash Memory Card (FMC) is the substrate for Flash Memory devices which store, read and write data easily.
 

Features

PSR surface planarization
Soft Au / hard Au plate & brightness
Substrate warpage control

Material BT Resin

Layer count 2~6

Line and Space 0.040mm / 0.040mm

Board Thickness 0.13mm

Surface Finish Hard Au 5um/0.5um, Soft Au 5um/0.3um

Others such as Sip packaging substrate,MEMS/CMOS packaging substrate,MiniLED substrate,LED chip package substrate,MCP substrate etc.

Applications:

Flash Memory Card/NAND memory,DRAM,DDR2,GDDDR4,GDDDR5,Microprocessors / controllers, ASICs, Gate Arrays, memory, DSPs, PLDs,Graphics and PC chip sets,Cellular, wireless telecommunications, PCMCIA cards,Laptop PC's, video cameras, disc drives, PLDs,

Mobile Application ProcessorBaseband,SRAM, DRAM, Flash Memory,Digital Baseband,Graphic Processor,Multimedia Controller,Application Processor.