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The technology allows the stacking of 12 DRAM chips using more than 60,000 TSV holes, while maintaining the same thickness as current 8-layer packages.

The thickness of the package (720㎛) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products.

This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs.

In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical,” says Samsung’s Hong-Joo Baek.

By increasing the number of stacked layers from eight to 12, Samsung will soon be able to mass produce 24GB HBM, which provides three times the capacity of 8GB high bandwidth memory on the market today.