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Dr. Jianying Peng graduated from Zhejiang University and is currently the executive president of Xinlai Technology. He is mainly responsible for the R&D and market management of RISC-V processors and other related products. She has many years of processor design related work experience. She used to be the senior R&D manager of Synopsys ARC processor and established the ARC China R&D center, and the R&D manager of Marvel ARM CPU department.

1. What are the main factors to consider when making SoC design planning

As a CPU IP supplier, we have observed from different customers that they mainly consider the following main factors when doing SoC design planning:

●Product definition and key technical indicators: General customers have targeted target markets and application scenarios, so early product definitions are relatively clear, such as CPU performance (frequency, DMIPS/CoreMark and other basic test scores) will be clear Scope requirements, list of other peripheral IP required, and frequency, area and power consumption of the overall chip.

●Hardware characteristics and overall architecture: Once the product definition is determined, the next step is to divide the software and hardware functions, determine the hardware module characteristics, and the overall SoC architecture (main bus structure). Determine the entire SoC architecture through specific applications and algorithm evaluation, including the bus structure, the number and connection of Master/Slave, the storage structure, and the specific characteristics of key IP modules. Take CPU as an example, do you need processing units such as DSP and FPU; storage structure (ICache/DCache, on-chip instruction tightly coupled SRAM, on-chip data tightly coupled SRAM) and capacity, and the required system bus structure.

●Software ecology and user habits: Software ecology and user habits are invisible and intangible, but they are essential to SoC design. Software development environment (IDE, SDK, etc.), basic tool chain (compiler, debugger, etc.), operating system support... These are all related to the efficiency and habits of software development of chip terminal customers.

●Comprehensive cost-effectiveness of time, manpower, and capital costs: High cost-effectiveness is a necessary condition for the success of commercial customers. Everyone hopes to complete the design and verification of SoC software and hardware in the shortest time and with the least amount of manpower. Of course, they also hope that IP costs, subsequent tapeouts, packaging and testing costs are the most reasonable prices.

Of course, the priority or weight of these factors will be different for each customer. Since its establishment 2 years ago, Xinlai Technology has witnessed RISC-V's landing in China. Initially, for the emerging RISC-V, most SoC design companies held a wait-and-see attitude because of the software ecology and user habits. With the vigorous development of the entire software and hardware ecosystem of RISC-V, now we see more and more customers start to choose RISC-V because of the advantages of cost-effectiveness, differentiated product definitions and flexible scalability.

2. What are the main criteria based on the current mainstream SoC when choosing processor core IP? How to achieve differentiated design?

There are indeed certain unified standards for the selection of processor IP during SoC design, such as hardware indicators, software indicators, stability, and price.

The hardware indicators mainly include:

●Under a specific process, frequency, area, power consumption parameter requirements, and typical CPU benchmark test scores (DMIPS, CoreMark, etc.);

●Different instruction set combinations, such as RISC-V 32-bit or RISC-V 64-bit instruction set, DSP, single and double precision FPU, etc.;

●Storage unit structure and size;

●The number and priority of interrupts, response speed, etc.;

●Supported bus interface type and clock frequency ratio, etc.

The software indicators mainly include:

●Perfect software development environment and development platform (IDE, SDK, etc.);

●Mature and stable tool chain (compiler, emulator, debugger, etc.);

●Standard software interface and rich algorithm software library, etc.;

● Friendly third-party software support ((Segger, IAR, Lauterbach, etc.);

●Mainstream operating system support (RTOS, Linux, etc.).

Stability is mainly because the CPU IP needs to be fully verified, and it must have sufficient robustness on different processes and test platforms. The price mainly includes authorization fees and subsequent support and maintenance costs.

How to provide customers with competitive and differentiated designs? This has always been the direction in which Xinlai Technology is exploring and working hard. At present, we mainly consider the following aspects:

1) Highly configurable processor IP

All core RISC-V CPU IPs include a wealth of configurable options. Customers can configure their required parameters through a graphical interface to meet performance requirements without wasting additional resources, such as the number of interrupts and priority, ICache/DCache size , Do you need on-chip instruction and data SRAM, the number of multiplication cycles, etc. Then generate the required code.

2) The scalability of the RISC-V instruction set (user-defined instructions)

In the RISC-V instruction set definition, part of the coding space has been reserved for user-defined instructions, and Nuclei Technology provides a NICE (Nuclei Instruction Co-Unit Extension) extension solution. The customer analyzes the algorithms that require hardware acceleration and defines the corresponding instructions according to the application in a specific field. Based on the core of the RISC-V processor microkernel, the NICE interface is reserved to realize the acceleration unit for the specific field. The acceleration unit can share storage and other resources with the processor microkernel, which can greatly improve the energy efficiency ratio, and can also help customers quickly develop products with differentiated architectures for specific fields.

3) Hardware acceleration module for subdivisions

For SoC designs in certain subdivisions, Sina Technology also provides different flexible hardware acceleration solutions, such as processor physical security enhancement modules, dual-core lockstep, vector modules, NPU modules, etc.

3. What new technologies and application trends in the SoC design field are worth paying attention to?

With the advent of the 5G and AIoT era, more and more intelligent application scenarios are born, and there is also a trend of "application and software-defined chip SoC design", which also puts forward new requirements for rapid product iteration. This means that SoC design needs:

●Solve the problems of specific practical scenarios more effectively

●Faster market response speed

●With feature differentiation and cost advantages

I think the current SoC design mainly has the following key trends:

●DSA (Domain Specific Architecture or Domain Specific Accelerator), a coprocessor accelerator for dedicated applications

The goal of DSA is to improve the energy efficiency ratio of computing, so it can better meet the differentiation, safety, and timeliness of SoC design to the market. How to achieve this goal? One of the core concepts is "specializing in the technical industry". In the hardware field, dedicated hardware is used to meet the needs of specific fields. But this is different from the general ASIC hardware. DSA needs to meet the needs of a field and solve a type of problem rather than a single problem, so it can achieve a balance of flexibility and specificity. As far as the processor field is concerned, DSA can be interpreted as Domain Specific Accelerator, that is, based on general processing, an accelerator for certain fields is expanded to improve the efficiency of solving problems in this field.

●Full-stack SoC design platform

The full-stack SoC design platform can greatly reduce the traditional SoC design cycle and design cost. The one-stop SoC platform can provide an overall solution for SoC software and hardware design, generally including basic common IP, SoC architecture, test cases, operating system, software drivers, algorithm libraries, development tools and other modules required for SoC design. At present, Singular Technology has launched a full-stack IP solution based on Singular’s ​​RISC-V processor for MCU, AIoT and other application fields, including a pre-integrated overall SoC template (including Singular’s ​​basic IP library, unified IP interface and bus structure, etc.), software and hardware drivers, NMSIS algorithm library, fully transplanted operating system examples, and Corelay’s own IDE/SDK and other development environments. Let customers ensure on-demand customization in SoC design, do not waste resources, help customers reduce R&D investment, and improve R&D efficiency and quality.

●chiplet new IP multiplexing mode

In the post-Moore's Law era, chip integration is getting higher and higher, and SoC design is becoming more and more complicated. In order to reduce the entire chip SoC design cycle and total development cost, Chiplet mode has become a popular trend. Chiplet is actually a die with certain functions. Based on the Chiplet model, first decompose the complex functions that need to be implemented, then develop or reuse existing dies with different process nodes, different materials, and different functions, and finally form a complete chip through SiP (System in Package) packaging technology . So Chiplet is a new IP multiplexing mode-provided in the form of chip die.

In addition to solving the problem of misalignment of digital circuits and analog or interface circuits on process nodes, Chiplet can also provide greater flexibility in SoC design. For example, some SoC designs have different requirements for the number of interfaces or analog channels in different scenarios. If they are all integrated on a die, they lack flexibility, and it is difficult to achieve optimal performance, function and area (also known as PPA). . Chiplet better solves the problem of flexibility in scenarios through digital and analog. Of course, chiplet also faces many challenges, such as interface standardization, and the huge amount of data between interfaces causes high power consumption caused by interconnection between dies and dies. And other issues.

4. What challenges does current SoC design face in terms of performance, power consumption and size? What is the solution?

With the slowing down of Moore's Law, the cost of advanced technology (28nm->22nm->14nm->7nm->5nm) continues to rise, SoC design can no longer only hope that the process node shrinks to meet the performance, function and area size requirements .

In SoC design, performance, function and area are often not satisfied at the same time, and we can only try to achieve a perfect compromise. For example, low-power technologies such as Clock Gating, Power Gating, and Multiple Power Domains are used without affecting performance, but the cost is that the area will be larger. Therefore, the PPA compromise strategy does not have a consistent standard, but a specific analysis based on the actual application.

Therefore, I think SoC design can only be designed on demand, and the challenge of PPA can be better solved when appropriate. Of course, this on-demand design is mainly reflected in the IP reuse support points mentioned above:

●Highly configurable multiplexing IP-different IP parameters can be flexibly configured according to PPA requirements, without wasting area and power consumption under the premise of meeting performance;

●Full-stack SOC design platform-According to PPA requirements, you can flexibly select the required IP modules, and use a unified IP interface to reduce the area and power consumption of IP interconnection; provide an overall solution for software and hardware, and further enhance software and hardware coordination Design, function division is reasonable, reduce hardware design complexity, etc.

5. What is the difference between the requirements for SoC design in the Internet of Things and edge computing fields and mobile computing/personal computers? How to choose the right processor core?

From personal computers to mobile computing (mobile phones), chip SOC design (including processor development) is mainly driven by single applications and key products. At present, with 5G, AIoT, edge computing and other application scenarios blooming, and there are no clear industry standards and specifications, the application scenarios are more diversified, the demand is more fragmented, the single product demand is moderate, and the innovation iteration becomes faster. There is also a need for faster market response. Therefore, the customization of chip SoC design has become a trend. As the entire control brain of the SoC, the processor, in addition to the traditional PPA hardware indicators, complete basic software tool chain and ecology, is more important to the flexibility and scalability of the processor to meet differentiation and diversification. Design, and the establishment of technical barriers.

ARM does not have absolute ecological advantages in these emerging fields. Therefore, RISC-V, which is open and has technical advantages such as simplicity, low power consumption, modularity, and scalability, will be promising in the fields of AIoT and edge computing and scenarios that require customization.

In addition to technical flexibility, RISC-V can also bring significant cost advantages to AIoT, edge computing and other fields. Semico Research, an international market analysis organization, pointed out in its report titled "RISC-V Market Analysis: Emerging Markets" that it is estimated that by 2025, the market will consume a total of 62.4 billion RISC-V CPU cores, and China will have the world's largest Market space.