June 30, 2022
Readers familiar with TSMC should know that the foundry giant has combined its 2.5D and 3D packaging products under one brand - "3D Fabric". As they expect, future customers will pursue both options to provide dense, heterogeneous integration of system-level functions—for example, "front-end" 3D vertical assembly combined with "back-end" 2.5D integration.
Technically, the 2.5D integration of a SoC with a "3D" high-bandwidth memory HBM stack is already a combined product. As shown above, TSMC is envisioning a richer combination of topologies in the future, combining 3D SoIC with 2.5D CoWoS/InFO as part of a very complex heterogeneous system design.
As with the process technology demonstrations at the workshop, the update of the packaging technology is very simple - it shows the success of its roadmap and only needs to be continued to execute, there are several specific areas that represent new directions we will highlight below.
Of particular note is TSMC's investment in an advanced systems integration facility that will support 3D Fabric products, providing full assembly and test manufacturing capabilities. According to TSMC, the world's first fully automated 3D Fabric advanced packaging factory in Zhunan is expected to start production in the second half of this year.
Why Focus on Advanced Packaging
In everyone's consistent understanding, TSMC is actually engaged in the foundry business. But entering the new century, whether it is TSMC, Samsung or even Intel, all take advanced packaging as a major focus of the company's work. in the results.
As reported by semiwiki, Moore's Law is no longer cost-effective for many other applications, especially for integrating heterogeneous functions, such as Multi-chip modules (MCM) and System in Package SiP, etc. "Moore than Moore" technology has emerged as an alternative to integrating a lot of logic and memory, analog, MEMS, etc. into a (subsystem) solution. However, these methods are still very client-specific and take a significant amount of development time and cost.
Looking at the history of chip development, in fact, the concept of advanced packaging has existed for decades. Compromising by assembling different and advanced chips in a package is one way to advance chip design. Today, this concept is sometimes referred to as heterogeneous integration. Nonetheless, due to cost reasons, advanced packaging is mainly used in high-end, niche-oriented applications.
But that may soon change. Because IC scaling is the traditional way of advancing designs, it shrinks the different chip functions at each node and packs them onto a monolithic chip. However, IC scaling has become too expensive for many, and the benefits per node are diminishing.
While scaling remains an option for new designs, the industry is looking for alternatives, including advanced packaging. What has changed is that the industry is developing new advanced packaging types or extending existing technologies.
The motivation behind advanced packaging remains the same. Rather than cram all chip functions onto the same chip, break them down and integrate them into a single package. This is said to reduce costs and provide better yields. Another goal is to keep the chips close to each other. Many advanced packs bring memory closer to the processor, allowing faster access to data with lower latency.
It sounds simple, but here are a few challenges. Also, there is no one package type that meets all needs. In reality, chip customers face a wide variety of options. Among them: Fan-Out (integrated die and components in wafer-level packaging), 2.5D/3D (chips placed side-by-side or on top of each other in a package) and 3D-IC: (stacking memory on top of memory, stacking on logic or Logically stacking logic) becomes three common choices.
In addition, the industry is also pursuing a concept called Chiplets, which supports 2.5D/3D technology. The idea is that you have a choice of modular chips or chiplets in the library. They are then integrated into a package and connected using a die-to-die interconnect scheme.
On the TSMC side, in order to meet market demand for new multi-chip IC packaging solutions, they are also working with their OIP partners to develop advanced IC packaging technologies to provide economical solutions for integration beyond Moore's Law.
In 2012, TSMC, along with Xilinx, introduced the largest FPGA at the time, consisting of four identical 28 nm FPGA chips mounted side-by-side on a silicon interposer. They also developed through-silicon vias (TSVs), microbumps, and re-distribution-layers (RDLs) to interconnect these building blocks. Based on its construction, TSMC named the integrated circuit packaging solution CoWoS (Chip-on-Wafer-on-Substrate). This block-based and EDA-enabled packaging technology has become the de facto industry standard for high-performance and high-power designs.
TSMC announced InFO (Integrated FanOut technology) technology in 2017. It uses polyamide film to replace the silicon interposer in CoWoS, thereby reducing unit cost and package height, both important criteria for the success of mobile applications. TSMC has shipped numerous InFO designs for smartphones.
TSMC introduced system-on-a-chip (SoIC) technology in 2019. With front-end (fab) equipment, TSMC can be very precisely aligned and then compression-bond designs using many narrow pitch copper pads to further minimize form factor, interconnect capacitance and power.
These two technologies have gradually evolved into today's 3D Fabric.
Latest Updates for 2022
As shown above, according to TSMC's plan, their packaging technologies now have 2.5D and 3D. Let's take a look at their 2.5D. According to reports, TSMC now has two types of 2.5D packaging technologies - "chip-on-wafer-on-substrate" (CoWoS: chip-on-wafer-on-substrate) and "integrated fanout" (InFO: integrated fanout). (Note that in the image above, some InFO products are represented as "2D" by TSMC.)
A key move for both technologies is the continued expansion of the maximum package size in order to integrate more dies (and HBM stacks). For example, fabricating an interconnect layer on a silicon interposer (CoWoS-S) requires “stitching” multiple lithographic exposures—the goal is to increase the interposer size by a multiple of the maximum reticle size.
Looking first at CoWoS, TSMC CoWoS has been expanded to offer three different interposer technologies (“wafers” in CoWoS), according to reports:
1. CoWoS-S: According to TSMC, in this packaging mode, a silicon interposer is used, based on existing silicon lithography and redistribution layer processing
▪️ Started mass production since 2012, so far more than 100 products have been supplied to more than 20 customers
▪️ Interposer integrates embedded "trench" capacitors
▪️ 3x maximum reticle size in development – supports design configurations with 2 large SoCs and 8 HBM3 memory stacks, and eDTC1100 (1100nF/mm**2)
2. CoWoS-R: In this packaging mode, an organic interposer is used to reduce cost
▪️ Up to 6 interconnect redistribution layers, 2um/2um L/S
▪️ 4x mask size, supports one SoC and 2 HBM2 stacks in 55mmX55mm package; 2.1X mask size is in development, 2 SoCs and 2HBM2 in 85mmX85mm package
3. CoWoS-L: Uses small silicon "bridges" inserted into organic interposers for high-density interconnects between adjacent die edges (0.4um/0.4um L/S pitch)
▪️ 2X reticle size supports 2 SoCs 2023 with 6 HBM2 stacks);
▪️ 4X reticle size in development to support 12 HBM3 stacks (2024)
TSMC emphasized that they are working with the HBM standards group on the physical configuration required for the HBM3 interconnect for CoWoS implementation. (For stack definitions, the HBM3 standard appears to have identified the following: 4GB capacity (4 8Gb dies) to 64GB (16 32Gb dies); 1024-bit signaling interface; up to 819GBps bandwidth.) These upcoming CoWoS configurations have Multiple HBM3 stacks will provide huge memory capacity and bandwidth.
Additionally, in anticipation of higher power consumption in upcoming CoWoS designs, TSMC is investigating suitable cooling solutions, including improved thermal interface material (TIM) between chip and package, and transition from air cooling to immersion cooling.
After introducing CoWoS, let's look at its InFO packaging technology.
It is understood that this packaging technique encapsulates the die in an epoxy "wafer" after accurate (face-down) orientation on a temporary carrier. A redistribution interconnect layer is added to the reconstructed wafer surface. The package bumps are then connected directly to the redistribution layer.
According to TSMC, the company's package has several topologies of InFO_PoP, InFO_oS and InFO_B.
As shown in the figure below, InFO_PoP represents a package-on-package configuration, focusing on the integration of the DRAM package with the underlying logic chip. The bumps on the top die of the DRAM use InFO vias (TIVs) to reach the redistribution layer.
TSMC said that InFO_PoP is mainly used for mobile platforms, and since the interview in 2016, the shipment of chips in this package has exceeded 1.2 billion. According to TSMC, in the current InFO_PoP mode, its DRAM package is a custom design, so it can only be manufactured at TSMC. To this end, TSMC is developing an alternative InFO_B topology that adds an existing (LPDDR) DRAM package on top and allows external contract manufacturers to provide assembly.
InFO_oS (on-substrate) can encapsulate multiple dies, and the redistribution layer and its microbumps are connected to the substrate through TSVs.
This is a technology that has been in production for over 5 years and is focused on HPC customers. From the technical details, the package has 5 RDL layers on the substrate with 2um/2um L/S. This allows the substrate to achieve a larger package size, currently 110mm X 110mm. According to TSMC, the company will plan to provide a larger size in the future - 130um C4 bump pitch
As for InFO_M, it is a replacement for InFO_oS with multiple package dies and redistribution layers without additional substrate + TSV (capable of < 500mm² package and will be produced in 2H2022).
After introducing TSMC's 2.5D packaging, we enter their 3D packaging world. Among them is a 3D package-on-package technology called InFO-3D, which utilizes microbumped chips vertically integrated with redistribution layers and TIVs, with a focus on mobile platforms.
As shown, TSMC also has a more advanced family of vertically-die-stacked 3D topology packages known as "systems on integrated chips" (SoICs). It utilizes direct copper bonding between the dies to obtain a very good pitch.
According to TSMC, the company has two SoIC products - "wafer-on-wafer" (WOW) and "chip-on-wafer" (COW). The WOW topology integrates a complex SoC die on the wafer, providing a deep trench capacitor (DTC) structure for optimal decoupling. A more general COW topology stacks multiple SoC dies.
Process technologies suitable for SoIC assembly are shown in the table below.
According to TSMC, the company's 3DFabric design support also includes 3Dblox. As shown in the upper right corner of the 3D Fabric image above, TSMC is envisioning a complex system-in-package design implementation combining 3D SoIC and 2.5D technology.
As mentioned above, this design flow is very complex and requires advanced thermal, timing and SI/PI analysis flows (which can also handle model data volumes). To support the development of these system-level designs, TSMC has collaborated with EDA suppliers on three main design flow initiatives:
The first of these includes the use of coarse-grained plus fine-grained methods for improved thermal analysis.
Second, TSMC and EDA giants are also collaborating on hierarchical static timing analysis. Let a single die be represented by an abstract model to reduce the complexity of multi-corne data analysis.
Finally, TSMC and the EDA giant also cooperated with the front-end design partition silly girl. 2 To help accelerate the front-end design division of complex systems, TSMC has also implemented a program called "3Dblox."
According to TSMC, the goal of the company's plan is to break down the entire physical packaging system into modular components and then integrate them. As shown, the module categories of the program are: bumps/bonds, vias, caps, interposers and die.
With this program, these modules will be integrated into any SoIC, CoWoS or InFO packaging technology.
Of particular note is that TSMC is working on enabling 3D Fabric designs to use a variety of EDA tools - that is, using one EDA vendor tool to complete the physical design and (potentially) using a different EDA vendor product to support Timing Analysis, Signal Integrity/Power Integrity Analysis, Thermal Analysis.
3Dblox appears to have taken the concept of "reference flows" for SoCs to the next level, with TSMC driving interoperability between EDA vendor data models and formats. 3Dblox's overall flow capability will be available in Q3 2022. (The preliminary steps—that is, automatic routing of redistribution signals on InFO—will be the first feature to be released.)
Clearly, due to the expected growth in 2.5D and 3D configurations, TSMC is investing heavily in advanced packaging technology development and (especially) new manufacturing facilities. The transition from the HBM2/2e to HBM3 memory stack will bring considerable performance benefits to system designs using CoWoS 2.5 technology. Mobile platform customers will expand the diversity of InFO's multi-chip designs. Adoption of complex 3DFabric designs combining 3D and 2.5D technologies will undoubtedly increase as well, leveraging TSMC's efforts to "modularize" design elements to speed up system partitioning, and their efforts to enable the use of a wide range of EDA tools/flows. .
Packaging Technology Fundamentals
According to TSMC's definition, front-end chip stacking technologies such as CoW (chip-on-wafer) and WoW (wafer-on-wafer) are collectively referred to as "SoIC", that is, System of Integrated Chips. The goal of these technologies is to stack silicon chips together without using the "bumps" seen on back-end integration options. Here, the SoIC design is actually creating the bonding interface so that the silicon can be placed on top of the silicon as if it were a single piece of silicon.
According to TSMC's official introduction, the company's SoIC service platform provides innovative front-end 3D inter-chip stacking technology for reintegration of small chips divided from system-on-chip (SoC). The final integrated chip outperforms the original SoC in terms of system performance. It also provides the flexibility to integrate other system functions. TSMC noted that the SoIC service platform addresses the ever-increasing computing, bandwidth and latency requirements in cloud, networking and edge applications. It supports CoW and WoW schemes, which provide excellent design flexibility when mixing and matching different chip functions, sizes and technology nodes.
Specifically, TSMC's SoIC technology is a very powerful method of stacking multiple dies into "3D building blocks" (aka "3D Chiplets").
Today, SoICs are capable of about 10,000 interconnects per square millimeter of space between vertically stacked chips. But the view is that this is developing work towards 1 million interconnects per square millimeter. 3D-IC enthusiasts have been looking for an IC packaging method that enables such fine interconnects, further reducing form factor, removing bandwidth limitations, simplifying thermal management in die stacks, and integrating large, highly parallel systems into them.
According to TSMC, one of the benefits of SoIC is its thermal performance. However, the downside of these SoIC technologies is that the stacked designs must be designed in conjunction with each other. Yet microbumping technology such as EMIB works in a way that can technically connect a series of chips together. With SoIC technologies like COW and WOWO, the design is fixed from the start.
Still, TSMC is keen to improve its SoIC chip stacking capabilities. According to TSMC's planning, this is a key technology for their future-oriented integration, which goes beyond the past implementation of interposer or chip stacking, because it allows silicon chips to be stacked without using any micro-bumps, but directly The metal layer of the silicon is aligned and bonded to the silicon chip.
Another relatively simple solution in packaging is to connect two silicon chips in one package. Typically, this is done with two silicon wafers side-by-side, with multiple connections. Most familiar to most is the interposer method, which places a large piece of silicon under all interconnected dies, and is a faster routing method than simply laying the traces through the PCB package.
Similarly, another approach is to embed an interposer in the PCB just to connect one specific die to another (this is what Intel calls its Embedded Multi-Die Interconnect Bridge or EMIB).
The third is direct die-to-die vertical stacking, however, because of the use of microbumps between the two silicon wafers, this is different from the SoIC implementation mentioned above - the SoIC uses bonding. Virtually all implementations in TSMC's products in the second half of the year are based on microbumps, as this allows for better mixing and matching of scenarios between different chips after each chip is fabricated, but doesn't get the density that SoIC offers or power advantage.
That's why it's called "post-segment" advanced encapsulation. This is how GPUs with HBM capabilities are implemented.
Many HBM enabled GPUs have one GPU die, several HBM dies, all placed on top of an interposer. GPUs and HBMs are made by different companies (and even different HBMs can be used), and silicon interposers can be made elsewhere. This silicon interposer can be passive (contains no logic, just die-to-die routing) or active, and can be designed for better network interconnections between chips if desired, Although this means that the interposer consumes power.
TSMC's GPU-like interposer strategy has been called CoWoS (chip-on-wafer-on-substrate) in the past. As part of 3DFabric, CoWoS now has three variants, divided by implementation:
The standard that everyone is familiar with is called CoWoS-S, where S stands for Silicon Interposer. The limitation of CoWoS-S is the size of the interposer, the termination is usually based on a 65nm fabrication process or similar. Since interposers are monolithic silicon wafers, they must be fabricated similarly, and as we move into the chiplet era, customers are demanding larger and larger interposers, which means TSMC must be able to manufacture them (and deliver high yields).
Traditional chips are limited by the size of the reticle, a fundamental limitation inside the machine, the size of one layer that can be "printed" on a single instance. To enable reticle-sized products, TSMC has been developing multi-reticle-sized interposer technology to make these products larger. Based on TSMC's own roadmap, we expect CoWoS implementations in 2023 to be around four times larger than the reticle, allowing more than 3000mm2 of active logic silicon per product.
The InFO package allows the chip to "fan out" to add additional connections beyond the standard SoC floor plan. This means that while the chip logic area can be small, the chip is larger than the logic circuit to accommodate all the necessary pin-out connections. TSMC has offered InFO for many years, but with the support of 3DFabric, it will now offer different types of InFO related to in-package connectivity.
The packaging technology of TMSC can also be combined in the same product. By implementing both front-end (SoIC) and back-end (InFO) packaging, new product categories can be fabricated. The company made a mockup like this:
On the face of it, TSMC will offer customers more packaging options in the coming years. Their main competitor in this area seems to be Intel, which has been able to implement its EMIB and Foveros technologies in some current products and some upcoming products. TSMC will benefit from working with more projects and customers.