April 28, 2021
In the post-Moore era, the performance enhancements produced by advanced processes are no longer sufficient to meet future application requirements. As ai (artificial intelligence) and hpc high-performance computing have become the focus of the semiconductor industry, the traditional semiconductor packaging technology that uses bumping or wirebond to connect the chip to the substrate has become the processor computing power The biggest bottleneck and source of power consumption for promotion.
2017-2023 Advanced Semiconductor Packaging Revenue Forecast
The focus of semiconductor innovation shifts to advanced packaging
Advanced semiconductor packaging is seen as a new way to increase the value of semiconductor products, increase functionality, maintain/improve performance, and reduce costs, such as system-in-package (sip) and more advanced packaging technologies in the future. However, with the expansion of semiconductor technology nodes, the birth of each new technology node is no longer as exciting as in the past, after all, a single technology can no longer produce the cost/performance improvement as in the past.
In terms of business model, the semiconductor packaging and testing industry is transforming from an idm model to an osat (package and test foundry) model. At present, osat has a market share of more than 50% in the packaging and testing market, and the concentration of the entire industry is constantly increasing.
In the Chinese market, the top three semiconductor packaging factories account for about 19% of the global osat industry, and the focus of their products is moving from the middle and low-end to the advanced packaging market.
Advanced semiconductor packaging landscape
At present, the leading manufacturers in the advanced packaging market include: large idm companies such as intel and samsung, four global osat manufacturers, and Taiwan Semiconductor Manufacturing Co., Ltd., a foundry and packaging company.
Among them, TSMC's packaging technologies include cowos, info pop integrated fan-out packaging, multi-wafer stacking (wafer-on-wafer, wow), and system-on-integrated-chips (soics) and so on.
Cowos, or chip on wafer on substrate, is TSMC’s first packaged and tested product. This technology puts the logic chip and dram on the silicon interposer, and then encapsulates it on the substrate.
Revenue of 25 top osat vendors from 2015 to 2017
Among the first-line packaging manufacturers, ASE has obvious advantages in the SIP field, and has maintained long-term cooperation with first-line design manufacturers such as Apple and Qualcomm. Amkor slim and swift bypass the high-cost tsv technology, and achieve 2.5d and 3d packages without sacrificing performance.
Among Chinese companies, Changjiang Electronics Technology has developed rapidly in the past few years, and has risen step by step in global competition with advanced technologies such as sip and ewlb; Huatian Technology has a multi-point layout, and its Tianshui plant focuses on low-end lead frame packaging and LED packaging. Tian Technology accounts for 53.7% of its total revenue. It has mid-range technologies such as card bit fingerprint recognition, rf, pa and mems in the Xi’an plant.
Shenzhen packaging plant believes that wafer fabs and packaging and testing plants are currently advancing the development of cutting-edge technologies such as sip, wlp, and tsv from different technical directions. At the same time, traditional packaging products such as plcc, pqfp, lccc, etc. commonly used in mos tube packaging, bridge stack packaging, and mosfet packaging will also maintain strong demand.